1. Field of this Invention
The present invention relates to a power-on reset circuit, which may include a reset-on state during power-up and/or power-down cycles of operation.
A power-on reset circuit may generate a power-on reset signal (hereinafter referred to as “POR signal”) for example, to enable operation of a semiconductor device system, when a power supply voltage reaches a certain level. If a voltage variation occurs during an initial operation state, the system may incur unexpected errors. The POR signal may protect the system from these types of errors. Therefore, a power-on reset circuit may be designed to delay a POR signal output until a power supply voltage has been activated.
2. Description of the Related Art
The configuration and operational characteristics of a conventional power-on reset circuit are illustrated in FIGS. 1 and 2.
Referring to FIG. 1, a conventional power-on reset circuit may include M PMOS transistors, MP1–MPM (M being a positive integer), resistors R1 and R2, N NMOS transistors, MN1–MNN (N being a positive integer), and an inverter IV1.
The PMOS transistors MP1–MPM may be serially coupled between a power supply voltage, for example VCC, and one end of the resistor R1. The gates of the PMOS transistors MP1–MPM may be connected to the drain of the PMOS transistor MPM and to one end of resistor R1, and the other end of resistor R1 may be connected to a voltage ground. The gates of the NMOS transistors MN1–MNN may also be connected to the drain of the PMOS transistor MPM, gates of the PMOS transistors MP1–MPM, and one end of the resistor R1. A connection node may be commonly connected to the drain of the PMOS transistor MPM, the gates of the PMOS transistors MP1–MPM, and one end of the resistor R1. One end of the resistor R2 may be connected to a power supply voltage, for example VCC, and the other end of R2 may be connected to an input port of the inverter IV1 and the drain of the NMOS transistor MN1. The inverter IV1 may be coupled to an output port for outputting a POR signal.
The operation of the power-on reset circuit illustrated in FIG. 1 will now be described with reference to FIG. 2, which illustrates a generation time for a POR signal that varies based on temperature.
A low-temperature characteristic illustrated by a fine line in FIG. 2 will now be described. As a power supply voltage VCC rises, a voltage signal POUT, corresponding to the connection node CN1 illustrated in FIG. 1, may increase to a low threshold voltage level VTNL illustrated in FIG. 2. VTNL corresponds to the threshold voltages of the PMOS transistors MP1–MPM, and is based on the rise of power supply voltage VCC. A difference between the power supply voltage VCC and the signal POUTL may be based on the body effect of the PMOS transistors MP1–MPM and VTNL.
A high-temperature characteristic illustrated by a bold line in FIG. 2 will now be described. If the voltage POUT of the connection node CN1, illustrated in FIG. 1, becomes higher than a high level threshold voltage VTNH corresponding to the NMOS transistors MN1-MNN, then each of the NMOS transistors MN1–MNN may be turned on. If each of the NMOS transistors MN1–MNN turn on, the inverter IV1 may output a power on reset signal ‘high’ PORH. The PORH signal may represent a higher turn-on speed due to a higher temperature, accordingly the PORH signal may be faster than the PORL by a time margin of ‘T1’. The PORH signal may be output from the inverter IV1 of FIG. 1 when a high temperature is activated, similarly the PORL signal may be output when a low temperature is activated.
Resistors R1 and R2 may have relatively high values when compared to a low standby current, and the transition time of a POR signal may depend on the threshold voltages of transistors. Since a threshold voltage of a transistor may vary with temperature, the transition time of the POR signal may also vary with temperature. Therefore, if the ambient temperature of the transistors is higher than expected then a POR signal may be generated before a power supply voltage rises, which may be required for regular system operation.
A conventional power-on reset circuit may consume extra power because standby current may be continuously generated from a power terminal even after generating a POR signal. If each node of a POR circuit is in a specific state or the effect of a parasitic capacitance is great, a POR signal may continuously increase with the rise of a power supply voltage, thus no reset signal may be generated.